History Of Computer Architecture First Generation Information Technology Essay

History Of computing machine data processor computer architecture initial Generation Information Technology EssayIn 1945 Electronic Numerical Integrator And Computer it was the first general purpose computer designed by Mauchly Echert, built by United States soldiery to calculateartilleryfiring tables for ballistic shells during World War II. The machine was developed using vacuum tubes and relays, and it was computer programmed to work manually by setting switches.UNIVersalAutomaticComputerI (UNIVAC) 1950 It was the first mercenary computer developed.John Von Neumann architecture Goldstine and Von Neumann took the idea of ENIAC and developed concept of storing a program in the retentiveness. Known as the Von Neumann architecture and has been the basis for practical(prenominal)ly every machine designed since then.FeaturesElectron emit devices information and programs are stored in a single read-write keepingMemory circumscribe are addressable by location, regardless of the content itselfMachine language/Assemble languageincidental exertionSecond Generation (1950-1964) TransistorsWilliam Shockley, John Bardeen, and Walter Brattain invent the transistor that reduce size of computers and improve reliability.First operating Systems handled wiz program at a timeOn-off switches controlled by electricityHigh direct languagesFloating point arithmeticThird Generation (1964-1974) Integ yardd Circuits (IC)Microprocessor chips combines thousands of transistors, entire circuit on one and only(a)(a) computer shipSemiconductor retrospectMultiple computer wayls with different performance characteristicsSmaller computers that did not need a specialized roomFourth Generation (1974-present) Very Large-Scale Integration (VLSI)/ immoderate Large Scale Integration (ULSI)Combines millions of transistorsSingle-chip processor and the single-board computer emergedCreation of the Personal Computer (PC)Wide penetrate use of info communicationsArtificial intellige nce Functions logic predicatesObject-Oriented programming Objects operations on objectsmassively collimate machine32 bit architectureIn computing 32 bit architecture refers to how a computer is build. In a 32 bit architecture computer the integer value stomach be stored in 32bits is 0 through 4,294,967,295 or 2,147,483,648 through 2,147,483,647 using 2s complement encoding. mess architectureIncomputer architecture a heaprefers to structure treatment data transmittal betwixt components inside acomputer frame, or computer network which transmit binary poem, one bit per wire. Modern computer buses can use both parallel and bit-serial connections, and can be pumped up(p) in either a electrical parallel ordaisy chaintopology, or connected by switched hubs, as in the scale ofUSB.A microprocessor communicates with memory and other devices (input and output) using three bussesAddress bus topologyData BusControl Bus.Address BusThe address busis acomputer bus, which harp series of lines connecting two or more devices that is used to specify aphysical address. When R3900processor call for to read or write to a memory location, it specifies that memory location on the address bus sent through thedata bus. The width of the address bus determines the amount of memory a system can address. In toshiba R3900 mainframe computer encumbrance address bus can address 232(4,294,967,296) memory locations which is 32bit. If to for each one one memory address holds one byte, the addressable memory space is 4 GB. Address bus is unidirectional, numbers only sent from microprocessor to memory, not other way.Data BusA data bus is acomputersubsystem that allows for the transferring of data from one component to another on amotherboardor system board. Data bus used to transmit data, information, results of arithmetic, etc, between memory and the microprocessor This can include transferring data to and from the memory, or from the exchange processing unit(CPU) to other compon ents, it is bi-directional. The R3900 data bus is designed to handle so many bits of data at a time. The amount of data a data bus can handle is called bandwidth. The toshiba 32 bits R3900processorcan transfer data through a data bus every second. At the same time they are devising data buses to handle more bits, they are besides making devices that can handle those higher bitratesControl BusAcontrol busis (part of) acomputer bus, used byCPUsfor communicating with other devices within the computer. The control bus will tell the memory that we are eitherreading from a location, specified on the address bus, or writing to a locationspecified. Various other signals to control and coordinate the operation of the system.The R3900 32 bit buss, which allow large number of educations, more memorylocation, and faster arithmetic. Microcontrollers organized along same lines, exceptbecause microcontrollers have memory etc inside the chip, the busses may all be national. In the microprocesso r the three busses are external to the chip (except for theinternal data bus). In external busses, the chip connects to the busses viabuffers, which are simply an electronic connection between external bus and theinternal data bus.Memory management unit(MMU)Memory management unit(MMU) is also called aspaged memory management unit(PMMU), is acomputer hardware component responsible for handling accesses tomemoryrequested by theCPU. Its functions include translation ofvirtual addressestophysical addresses(i.e.,virtual memorymanagement),memory protection,cachecontrol,busarbitration, and, in simpler computer architectures, bank switching.The functions performed by the memory management unit can typically be divided into three areashardware memory managementoperating systemmemory managementapplication memory managementThe Toshiba R3900 Processor Core Operating ModesThe R3900 Processor Core has two operating modessubstance abuser modekernel modeIt operates in the user mode normally, when exception is sight it changes to kernel mode. In kernel mode, it insures until an RFE (Restore from Exception) instruction is put throughd. The existing virtual address space varies with the mode.User modeUser mode exist only one of the two 2 Gbyte virtual address spaces (kuseg). The to the highest degree considerable bit of each kuseg address is 0. The range virtual address kuseg is of 0x0000 0000 to 0x7FFF FFFF. Attempting to access an address when the mutual savings bank is 1 while in user mode returns an Address Error exception. nucleus modeKernel mode makes available a second 2 Gbyte virtual address space (kseg), in auxiliary to the kuseg accessible in user mode. The range virtual address kuseg is of 0x8000 0000 to 0xFFFF FFFF.Direct Segment MappingThe Toshiba R3900 Processor Core has a direct segment mapping MMU.User modeOne 2 Gbyte virtual address space (kuseg) is available in user mode. In this mode, the most important bit of each kuseg address is 0. The virtual address range of kuseg is 0x0000 0000 to 0x7FFF FFFF. Attempting to access an address outside of this range, that is, with the MSB is 1,while in user mode will raise an Address Error exception. Virtual addresses 0x0000 0000 to 0x7FFF. FFFF are translated to physical addresses 0x4000 0000 to 0xBFFF FFFF, individually. The swiftness 16-Mbyte area of kuseg (0x7F00 0000 to 0x7FFF FFFF) is reserved for on-chip resources and is not cacheable.Kernel modeThe kernel mode address space is ta as four virtual address segments. One of these, kuseg, is the same as the one in user mode the other remaining three are kernel segments kseg0, kseg1 and kseg2.Pipeline ArchitectureComputer blood lineis a set of data processing parts connected in series, so that the output of one element is the input of the next one. The elements of a blood are often executed in parallel or in time-sliced fashion in that case, some amount ofbuffer storageis often inserted between elements.Each cycle different instruction is ex ecuted in different stagesFor example, 5-stage ancestry (Fetch-Decode-Read-Execute-Write),The Toshiba R3900 Processor Core executes instructions in five pipeline stages (F instruction fetch D decode E execute M memory access W register write-back).The five stages have the following roles.F An instruction is fetched from the instruction cache.D The instruction is decoded. Contents of the general-purpose registers are read..E Arithmetic, logical and shift operations are performed. The execution of multiple/divide instructions is begun.M The data cache is accessed in the case of load and store instructions.W The result is written to a general register.Each of the above pipeline stage is executed in one clock cycle. When the pipeline is fully used, the five instructions are executed at the same time, which will be resulting in an average instruction execution rate of one instruction per cycle.Delay SlotThe R3900 Processor Core instructions are executed with a discipline of one inst ruction cycle. Delay slot is the cycle in which an instruction is delayed. A delay occurs with load instructions and branch/jump instructions.Delayed loadDelayed branchingNon blocking essence FunctionIn the R3900 processor the non blocking load function stops the pipeline from stalling when a cache miss happens and a refill cycle is needed to refill the data cache. Instructions after the load instruction that do not use registers involved by the load will continue to be executed.Multiply and Multiply/Add Instructions(MULT, MULTU, MADD, MADDU)The R3900 Processor Core is able to execute procreate and multiply/add instructions continuously, and able to use the results in the HI/LO registers in immediately following instructions, without pipeline stall. The processor requires only one clock cycle to use the outcome of a general-purpose register. dissociate Instruction (DIV, DIVU)The Processor Core performs division instructions in the division unit independently of the pipeline. socio -economic class starts from the pipeline E stage and takes 35 cycles.StreamingThe R3900 Processor Core can resume execution immediately after arrival of necessary data or instruction in cache pull down though cache refill operation is not completed during a cache refill operation. This is referred to as streaming.